This application relates in general to network computer systems, and in specific to mechanism for initializing credit in a queue flow control system.
The communication between different nodes in a network computer system occurs in a producer-consumer fashion. A sender or producer node sends a transaction to one or more destination or consumer node(s). Each destination node stores the transaction in an internal queue and xe2x80x98consumesxe2x80x99 it at a later point of time. For example, in a multiprocessor system, a snoop request by the source node is stored in an internal queue by all the destination nodes. Each node will act on that snoop request at some later point in time, and then removes the request from its queue. Thus, a producer should not send a transaction to a destination node that does not have the space required to store the transaction in its queue. The space requirement is ensured by the underlying flow-control mechanism.
The flow-control mechanism may be reactive or proactive. In the reactive approach, the destination node tracks its own queues and sends a queue_full signal to the respective sending nodes when the queues are filling up. However, the proactive flow-control mechanism is considered to be more useful in systems with a point-to-point interconnect topology, for example cross-bar, ring, mesh, or hypercube. In the proactive approach, the sender node keeps track of the amount of available queue space in the destination node through the amount of xe2x80x98creditsxe2x80x99 it has for the corresponding queue in the destination node. Each credit translates to a certain number of entries in the destination queue. The number of available credits is maintained in a register in the sender node. This extra space register is referred to as no_credit. Each node will have one no_credit register for every queue in every destination node to which the node can send a transaction. A sender does not send a transaction if the amount of space required by the transaction is more than the number of credits it possesses for the queue in the destination node.
The destination node xe2x80x98releasesxe2x80x99 these credits to the sender, when it xe2x80x98consumesxe2x80x99 a transaction from its queue. A destination node may choose to release credits as it is unloading a transaction. Or the destination node may release the credits after the transaction has been unloaded. The amount of credits released by the destination node corresponds to the amount of space freed up in the queue by consumption of a transaction. The destination node keeps track of the amount of queue space it will be releasing in a debit register. This register is referred to as no_debit. The destination node releases the credits from the no_debit register when it gets an opportunity to send a transaction to the sender node that had sent the transaction(s) earlier. Note that the destination node may append the credits onto another transaction passing through the sender node.
After releasing credits, the no_debit register is decremented by the amount of credits released. On receipt of these credits, the sender adds the credits to the amount of credits available, no_credit, for that destination node. This way the sender keeps track of the amount of queue space it can safely use in the destination node for forwarding transactions.
Note that each node many have more than one queue associated with another particular node. For example, each node may have a request queue and a response queue to store requests and responses from another node. Therefore, separate credits will be maintained for each queue by the node.
A problem occurs with the initialization of credits in the no_credit and no_debit registers, either during an initial start up or after a reset. Different components of the system may undergo different design revisions and the corresponding queue sizes may change over time for the same component. Thus, the sender nodes cannot be hardwired to assume the queue size in the destination nodes since that size may change with changes made to the components of the destination node.
Therefore, during power up, the sender does not know how many credits to allocate in the registers for each queue in the destination node. The prior art uses a software mechanism with additional hardware to perform a credit initialization. Both the credit and debit registers are set to zero. The software is used to read the maximum number of credits for each destination node, and then write that into the sender node. However, in order to perform this credit initialization transaction credits must be available. Thus, this forms a paradox where a credit initialization cannot take place until credits are available. To solve this problem, the prior art uses a xe2x80x98power on modexe2x80x99 which allows all transactions to be sent without using credits. This mode requires extra logic and imposes a certain minimum queue sizing to allow for the reading and writing of registers. Thus, the prior art mechanism requires the user to have extensive knowledge of the system.
Therefore, there is a need in the art for a mechanism that allows for credit initialization without involving software intervention and using additional hardware.
These and other objects, features and technical advantages are achieved by a system and method which employs the mechanisms already in place and used for normal operations. During normal operations, if the sender has credits, then is may send transactions to the destination node. If the destination node has debits, then it releases them back to the sender node. During initialization, the credit register, no_credit, is loaded with a zero. Thus, the sender node begins operations with no credits, and cannot send any transactions. The debit register, no_debit, is loaded not with zero, but with the maximum credits representing the size of its queue. Thus, the destination register begins operations with the debit register full, and through normal operations, releases the credits back to the sender node. Thus, the sender node will then have credits and can then send transactions, and the destination node will have an empty debit register. This results in faster boot times, since the initialization is completed as soon as the chips are out of their reset state, which is 1 cycle after reset is withdrawn, because no time is spent on software operations in a start-up mode.
It is a technical advantage of the invention to perform initialization of the queue registers through normal flow control operations.
It is another technical advantage of the invention to eliminate the need for software credit initialization.
It is a further technical advantage of the invention to eliminate the need for additional hardware and registers for a power on mode.
It is a further technical advantage of the invention to have faster boot times, since the initialization is completed as soon as the chips are out of their reset state or 1 cycle after reset is withdrawn.
It is a further technical advantage of the invention that the inventive mechanism will work with any sized queue and does not have any minimum sizing requirements for initialization.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.